1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device for storing information with use of a change of a state of an electric fuse (an anti-fuse), which will also be abbreviated as “AF”, employing a breakdown of an oxide film.
2. Description of Related Art
The storage capacity of a memory semiconductor memory device as represented by a DRAM (Dynamic Random Access Memory) increases year and year along the progress of micro-fabrication techniques. The number of defective parts included per one chip also increases as miniaturization is proceeded.
Semiconductor memory devices are therefore provide with both normal memory cells, which are memory cells for normal use, and redundant memory cells, which substitute when a defect occurs in a normal memory cell. The defect remedy technology for replacing normal memory cells in which defects has been detected (hereinunder referred to as “defective memory cells”) with redundant memory cells to improve product yield has become a crucial technology.
In this connection, the defective memory cells are also called “defect memory cells”. Inasmuch as each memory cell corresponds to a bit, the defective memory cells are also called “detective bits”.
In order to replace a defective memory cell with a redundant memory cell, the address of the defective memory cell (hereinunder referred to as “fail address”) must be stored. The fail address is also called a “defective address”.
Laser fuses and the electric fuses (anti-fuses) (AFs) are used as nonvolatile memory elements for storing fail addresses. The laser fuse comprises a fuse in which a conductor is fused and insulated by a laser. The anti-fuse comprises a fuse in which a high voltage is applied to an insulator such as an oxide film to break down the insulator to cause conduction.
The fuses used as such as a method of repairing the defective memory cells of the DRAM has been moved to the anti-fuses from the laser fuses. This is because there are large merits for example no need of an opening process for the laser fuses, reliability improvement of moisture resistance or the like, no need of a process management of a remaining thickness on the laser fuses, passableness of metal wires on the fuses, and so on.
In the manner well known in the art, the AF is a method of storing the fail addresses of the detective bits by applying (carrying out connection operation) the high voltage to a gate oxide film or a memory cell film to control conducting/non-conducting thereof. This information is held after a power supply voltage is shut down.
Inasmuch as connection of the AF is an operation which actively breaks down the gate oxide film, it is an approach which is opposite to a concept of the reliability (high breakdown voltage) of the gate oxide film, and it is therefore difficult to control a breakdown.
JP-A-2007-116045 (which corresponds to US 2007/0091662 A1 and which will later be called “Patent Literature 1”) proposes several methods related to electric fuses (anti-fuses) mounted on a semiconductor device.
The following analysis is obtained in terms of this invention based on experience of the present inventor.
FIG. 4 of Patent Literature 1 (FIG. 6 of US 2007/0091662 A1) discloses an “OR cell scheme” for storing one bit by two AF cells (which will later be called a “Conventional Example 3”). However, an increase of an area becomes issue in the OR cell scheme.
FIG. 7 of Patent Literature 1 (FIG. 2 of US 2007/0091662 A1) discloses an “OR withdrawn scheme” for storing one bit by one AF cell (which will later be called a “Conventional Example 2”). The OR withdrawn scheme is effective to downsizing of an area so as to reduce the area by about fifty-three percent as compared with the above-mentioned OR cell scheme, and it is therefore possible to resolve the problem of the above-mentioned OR cell scheme. However, the OR withdrawn scheme has a bad feature of dropout or failure bits of the AF cell after connection, and the problem arises because it is difficult to improve connection yield. It is necessary for the OR withdrawn scheme to prolong the connection time interval up to 20 milliseconds or more.
FIG. 1 of Patent Literature 1 (FIG. 3 of US 2007/0091662 A1) discloses a “twin cell scheme” which is a scheme for storing one bit by two AF cells connected in parallel (which will later be called a “Conventional Example 1”). The twin cell scheme reduces the area by about forty-nine percent as compared with the above-mentioned OR cell scheme and it is therefore possible to resolve the problem of the above-mentioned OR cell scheme (the increase of the area). In addition, the twin cell scheme has an increased area as compared with the above-mentioned OR withdrawn scheme.
At this point, it may be understood that the twin cell scheme is an optimum scheme among their three schemes as the middle means in which the problem of the above-mentioned OR cell scheme (the increase of the area) is suppressed to some extent and the problem of the above-mentioned OR withdrawn scheme (the connection yield) is resolved.
However, in the manner which will later be described with reference to drawings in detail, it is understood, as result of carrying out an experiment by the present inventor, that yield of the twin cell scheme are equal to the OR withdrawn scheme and it does not have the effect of the yield at all.